PIPELINED SYNCHRONOUS STATIC RAM

نویسندگان

چکیده

برای دانلود باید عضویت طلایی داشته باشید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Testing of a GaAs MESFET Static RAM

This paper describes the complete test, functional and parametric, of a 1Kb GaAs MESFET SRAM chip. The chip was developed as an evaluation vehicle for a new type of MESFET SRAM cell. The new cell, in contrast with conventional GaAs memory cells, minimizes the leakage current in access transistors of unselected cells. Two algorithms were selected for functional testing: MATS and Galloping Ones a...

متن کامل

A Minimum Leakage Quasi-Static RAM Bitcell

As SRAMs continue to grow and comprise larger percentages of the area and power consumption in advanced systems, the need to minimize static currents becomes essential. This brief presents a novel 9T Quasi-Static RAM Bitcell that provides aggressive leakage reduction and high write margins. The quasi-static operation method of this cell, based on internal feedback and leakage ratios, minimizes ...

متن کامل

Dynamic Stabilization of Wind Farms Deploying Static Synchronous Series Compensator

Encountering series-compensated transmission lines, sub-synchronous resonance (SSR) may strike the power system by jeopardizing its stability and mechanical facilities. This paper aims to verify the capability of static synchronous series compensator (SSSC) in mitigating the mechanical and electrical oscillations such as SSR in wind farm integrations. A wind turbine with a self–excited inductio...

متن کامل

Synchronous Performance and Reliability Improvement in Pipelined ASICs

The clock frequency of a synchronous circuit can be increased at the expense of increased system latency, area, and power using synchronous optimization techniques such as pipelining and retiming. Pipelining is a well developed methodology, having been applied to almost every computer architecture from microprocessors to supercomputers. Retiming, on the other hand, has only recently become popu...

متن کامل

Design of synchronous and asynchronous variable-latency pipelined multipliers

This paper presents a novel variable-latency multiplier architecture, suitable for implementation as a self-timed multiplier core or as a fully synchronous multi-cycle multiplier core. The architecture combines a 2 order Booth algorithm with a split carry save array pipelined organization, incorporating multiple row skipping and completion-predicting carry-select final adder. The paper reports ...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: ELECTRONICS: Science, Technology, Business

سال: 2019

ISSN: 1992-4178

DOI: 10.22184/1992-4178.2019.184.3.130.136